1. Field of the Invention
The present invention relates to a common buffer memory control apparatus such as an ATM switching system, and more particularly to a common buffer memory control apparatus applied to a message communication service in which message data formed of a plurality of cells is transmitted.
2. Description of the Related Art
An ATM switching system operated in an Asynchronous Transfer Mode is used in a broad-band integrated services digital network (B-ISDN). In such an ATM switching system, a switching apparatus using a common buffer memory carries out a routing operation for cells in an ATM network.
A conventional switching apparatus using the common buffer memory controls, using address chains, a read/write operation of the common buffer memory. FIG. 1 shows a conventional switching apparatus using the common buffer memory.
Referring to FIG. 1, the switching apparatus has a multiplexing unit (MUX) 31, a common buffer memory 32, an address pointer 33, a demultiplexing unit (DEMUX) 34, a routing information decoder (RTGDEC) 35, a writing address memory 36, a reading address memory 37, an output route number decoder 38 and an output route number counter 39. The address pointer 33 specifies reading and writing points in the common buffer memory 32.
The writing address memory 36 has memory areas WA-1 to WA-n each of which corresponds to one of output routes. The reading address memory 37 has memory areas RA-1 to RA-n each of which corresponds to one of the output routes.
Cells input from respective input lines (input-1˜input-n) are multiplexed by the multiplexing unit 33 and output to the common buffer memory 32 cell by cell. The multiplexing unit 31 extracts routing information stored in a header portion of each cell. The routing information is then supplied to the routing information decoder 35. The routing information decoder 35 decodes the routing information and specifies a writing address memory area WA-i corresponding to an output route number i obtained by decoding the routing information.
The respective writing address memory areas WA-1˜WA-n, corresponding to the output routes, stores writing addresses for cells in the common buffer memory 32. The writing address memory area WA-i specified by the routing information decoder 35 outputs a writing address stored therein to the address pointer 33.
The common buffer memory 32 stores a cell received from the multiplexing unit 31 at an address specified by the address pointer 33. In addition, when the next cell for the same output route is received, the address pointer 33 outputs an address at which the cell should be stored to the writing address memory area WA-i so that the contents of the writing address memory area WA-i is updated to the new address.
On the other hand, the cell written in the common buffer memory 32 is read out therefrom as follows. The output route number counter 39 successively outputs output route numbers in order. The output route number decoder 38 specifies a read address memory area RA-i corresponding to an output route number i.
The respective read address memory areas RA-1 to RA-n corresponding to the output routes store addresses of the common buffer memory 32 at which cells to be transmitted are stored. The read address memory area RA-i specified by the output route decoder 38 outputs an address stored therein to the address pointer 33. A cell stored at the address specified by the address pointer 33 is read out from the common buffer memory 32 and supplied to the demultiplexing unit 34.
In addition, the address pointer 33 outputs an address at which a cell to be next transmitted to the output route has been stored to the read address memory area RA-i. The contents of the read address memory area RA-i is thus updated to the new address.
When the cell is read out from the common buffer memory 32 and output to the demultiplexing unit 34, the area (address) of the common buffer memory 32 in (at) which the cell has been stored is opened. After this, the area of the common buffer memory 32 is used to write a cell received later.
The cells read out from the common buffer memory 32 are routed to output routes, by the demultiplexing unit 34, in accordance with routing information in the header portions of the cells. The cell are then output to corresponding output lines (output-1˜output-n).
When the so-called message communication service in which a single message data item formed of a plurality of cells is transmitted is supported by using a such conventional switching apparatus as described above, the single message data item is stored in the common buffer memory 32 so as to be divided in to a plurality of cells.
Thus, in handling of the message data between the ATM layer and the upper layer, all addresses at which the respective cells of the single message data item should be processed. As a result, the process is complex and the quick supply of the message communication service deteriorates.